Technical Field
The present disclosure relates to statistical timing analysis of integrated circuit designs, and more specifically, to statistical timing analysis using statistical-timing macro-models while considering statistical timing value entries such as statistical input slew and statistical output load.
Related Art
Static timing analysis (STA) is used to compute the expected timing of a digital circuit to identify problem areas of an integrated circuit during the design phase and in advance of actual fabrication. Timing runs in STA simulate the timing of the integrated circuit to determine whether or not the integrated circuit meets various timing constraints and, therefore, is likely to operate properly if fabricated in accordance with the tested design.
Deterministic static timing analysis (DSTA) propagates timing value entries, such as arrival times (ATs), required arrival times (RATs), and slews, along with any other timing related quantities (guard times, adjusts, asserts, slacks, etc.), in a timing graph as single valued deterministic data. DSTA covers a single corner of a space of process variations with each individual timing run. A corner represents a particular combination of input values for a parameter that may include temperature of the circuit, input voltage, and various manufacturing parameters of an integrated circuit. To evaluate the impact that a given parameter will have on timing, multiple DSTA timing runs must be executed with parameters that affect timing set at several maximum and minimum corners, such as high and low temperature, high and low voltages, and various processing conditions. For example, DSTA timing runs may compare a worst case corner characterized by a combination of high input voltage, a high operating temperature, and the worst manufacturing parameters with a best case corner characterized by a combination of a low input voltage, a low operating temperature, and the best manufacturing parameters.
Timing values are computed for a timing graph at each node based upon the ATs, which define the time (or the time distribution) at which a given signal arrives at a timing point, and the RATs, which defines the time (or the time distribution) at which the signal is required to get to the timing point, in order to meet the timing requirements. These ATs and RATs are used to compute timing metrics in the form of slacks at nodes (RAT minus AT for late mode and AT minus RAT for early mode). A negative value for either a late mode slack or an early mode slack indicates a timing constraint violation. As a check of the performance of the integrated circuit design, DSTA timing runs may examine many or all of the corners and the IC design may be iteratively adjusted until all of the corners pass the timing tests. These results reflect the extreme performance bounds of the integrated circuit and may require numerous timing runs to fully explore the space of process variations. Even then, the results may be overly pessimistic and misleading for optimization tools.
Statistical static timing analysis (SSTA) propagates timing value entries as random variables with known probability distribution functions, or their approximation, instead of as single valued deterministic data under DTSA. SSTA may calculate a result, for example, a delay and/or output slew, for the propagated statistical distribution functions of input slew and (output) load. A single timing run using block-based SSTA predicts the performance of the integrated circuit over the entire space of process variations. In contrast, a single timing run using DSTA merely predicts a single corner of the space of process variations. Consequently, in order to close timing, a single SSTA timing run may replace multiple DSTA timing runs. For example, assuming the existence of N parameters (i.e., variables or sources of variation) and two corners per parameter, 2N corners would have to be individually analyzed by discrete DSTA timing runs to match the effectiveness of a single SSTA run. Hence, SSTA is far more computationally efficient than DSTA.
A test run that passes in a single process corner under a DSTA timing run may actually fail without detection in one or more other performance-limiting corners in the process space, which a SSTA timing run would reveal. SSTA also reduces pessimism as a result of the statistical techniques inherent in this approach. For example, the propagation of known independently random terms in SSTA allows for taking the square root of the sum of the squares of random quantities (RSSing) between each propagation state, rather than straight summation as in DTSA. Other pessimism relief may occur when sampling the final distributions, as additional RSSing may occur between terms during projection from a distribution to some example sample value. Finally, information regarding the probability of particular failure modes may be obtained in SSTA, as opposed to DSTA that merely indicates a binary pass/fail condition. SSTA may allow for very low probability fails to be ignored while also allowing for a more aggressive clipping of the statistical tails when used with at-speed tests.
With increasing significance of variability in the chip design and manufacturing process, SSTA is increasingly employed during IC design finalization. Variability can include any parameter that can change how integrated circuit performs. Examples of variability include fabrication process variability such as line width; operational variability such as internal temperature or voltage; environmental variability such as external temperature; etc. For large designs, timing is typically carried out in a hierarchal manner, e.g., evaluating multi-core chips, multi-unit cores, and then multi-macro units. Parts of the timing methodology may include, for example, transistor or gate level timing of macros, timing abstraction (macro-modeling) and gate level timing at parent levels of hierarchy (e.g., unit, core, chip). To handle large designs, design partitions (e.g., macros, units) are designed and timed in isolation (“out of context”) and then abstracted (macro-modeled). These macro-models are subsequently used at the parent level of hierarchy. In order to capture the impact of variability in these macro-models, statistical macro-modeling (statistical abstraction) is performed. Statistical timing macro-models contain timing information (like statistical delays, statistical output-slews, statistical test-margins, etc.) which are often stored as lookup-tables as a function of inputs such as deterministic input-slew and deterministic output-load samples. For example, where values of an input slew (s) at a point A in an integrated circuit and a particular output load (l) at point B in an IC are both deterministic, a look up table of the corresponding statistical delay D(s,l) can be easily calculated. In this setting, the statistical delay D(s,l) for deterministic input-slew (s) and deterministic output load (l) can be represented by the equation:
                              D          ⁡                      (                          s              ,              l                        )                          =                              μ            ⁡                          (                              s                ,                l                            )                                +                                    ∑                              i                =                1                            N                        ⁢                                                            a                  i                                ⁡                                  (                                      s                    ,                    l                                    )                                            ⁢                              X                i                                              +                                    ∑                              i                =                1                                            N                -                1                                      ⁢                                          ∑                                  j                  =                                      i                    +                    1                                                  N                            ⁢                                                                    a                    ij                                    ⁡                                      (                                          s                      ,                      l                                        )                                                  ⁢                                  X                  i                                ⁢                                  X                  j                                                                                        Equation        ⁢                                  ⁢        A            
where μ(s,l) represents a nominal value of the delay (D) which denotes the value of delay in the absence of any variations; ai(s,l) represents an intrinsic linear timing sensitivity of delay due to a single source of variation Xi; aij(s,l) represents a cross-term timing sensitivity of delay due to sources of variation Xi and Xj; and N is the number of sources of variation. In a deterministic model, each of the above values can be calculated and provided in simple look up tables. A statistical timing quantity can be projected to a deterministic value by assigning a numeric corner value for each source of variation Xi. As an example, if all sources of variation except Xk are at their base corner values (denoted by Bi for Xi), and Xk is at a non-corner value Ok, the projected value of D is given by:
                              μ          ⁡                      (                          s              ,              l                        )                          +                              ∑                                          i                =                1                            ,                              i                ≠                k                                      N                    ⁢                                                    a                i                            ⁡                              (                                  s                  ,                  l                                )                                      ⁢                          B              i                                      +                                            a              k                        ⁡                          (                              s                ,                l                            )                                ⁢                      O            k                          +                              ∑                                          i                =                1                            ,                              i                ≠                k                                                    N              -              1                                ⁢                                    ∑                                                j                  =                                      i                    +                    1                                                  ,                                  j                  ≠                  k                                            N                        ⁢                                                            a                  ij                                ⁡                                  (                                      s                    ,                    l                                    )                                            ⁢                              B                i                            ⁢                              B                j                                                    +                              ∑                          j              =                              k                +                1                                      N                    ⁢                                    a              kj                        ⁢                          O              k                        ⁢                                          B                j                            .                                                          Equation        ⁢                                  ⁢        B            
If the base corner for each source of variation is assumed to be 0, the projected value of D is given by:μ(s,l)+ak(s,l)Ok.  Equation C
A challenge with the conventional deterministic approach is that timing value entries, such as input-slew and output-load, are variability dependent. In other words, they can be considered a statistical distribution. For example, the fact that an output load is fabrication process, voltage, temperature (PVT) dependent indicates that loads can be modeled in a statistical fashion. Consequently, statistical timing value entries such as input slews and output loads introduce a new dimension of complexity in statistical macro-modeling. While traditional deterministic macro-models contain deterministic timing quantities (e.g., delays, output-slews, etc.) as a lookup table of deterministic timing value entries like input-slew and/or load, it is unclear if statistical macro-models should have lookup tables as a function of deterministic timing value entries (e.g., deterministic input-slew and deterministic output-loads) or statistical timing value entries (e.g., statistical input-slew and statistical output-loads). While the latter is the seemingly more proper method, it increases the lookup table size enormously (distribution inputs and distribution outputs) and, therefore, can be impractical for use. On the other hand, if, for example, the statistical macro-model lookup tables are characterized using deterministic timing value entries (slews and/or loads), it is important to model the impact of the input-slew's and load's variability when the macro-model is used at the parent level of hierarchy. Based on the complexity of the statistical calculation of the illustrative timing value entries, it becomes very difficult to determine a statistical timing quantity result such as delay.
A simple approach to the above-described challenge is to use the mean value (or some projected value of the given statistical input slew Sin and statistical load L) to get a deterministic input-slew and load, and then use these values for table-lookup in a statistical timing macro-model. However, this approach is inaccurate and can cause significant timing inaccuracy. An alternate approach is to expand the statistical macro-model into multiple deterministic macro-models at different corners of variability, and use the various deterministic macro-models for statistical timing using finite-differencing. While this latter approach has no conceptual loss in accuracy, it causes undesired run-time increases. For example, current solutions to the variability aware macro-modeling include generating multiple deterministic models at different conditions (or corners) of variability. This approach suffers from “corner explosion”; that is, the need to close timing at too many corners, which is inefficient and may delay a chip's time to market in comparison with statistical timing based IC design finalization.